The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field.
The GOA technology, i.e. the Gate Driver on Array technology utilizes the original array manufacture processes of the liquid crystal display panel to manufacture the driving circuit of the level scan lines on the substrate around the active area, to replace the external Integrated Circuit (IC) for accomplishing the driving of the level scan lines. The GOA technology can reduce the bonding procedure of the external IC and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products.
With the development of the LTPS semiconductor TFT, the LTPS-TFT LCD also becomes the focus that people pay lots of attentions. The LTPS-TFT LCD possesses advantages of high resolution, fast response speed, high brightness and high aperture ratio. Because the LTPS semiconductor has better order than amorphous silicon (a-Si) and the LTPS itself has extremely high carrier mobility which can be more than 100 times of the amorphous silicon semiconductor, which the GOA skill can be utilized to manufacture the gate driver on the TFT array substrate to achieve the objective of system integration and saving the space and the cost of the driving IC.
FIG. 1 shows a GOA circuit employed in the LTPS liquid crystal display device according to prior art, comprising GOA units of a plurality of stages. The GOA circuit of prior art does not only possess the fundamental scan driving function and the shift register function, but also the function of outputting the scan driving signals for all the respective stages at the same time (All Gate On). The GOA unit of each stage comprises: a control input unit 100, a voltage stabilizing unit 200, an output control unit 300, a second node control unit 400, a first node pull-down unit 500, a pull-down holding unit 600, a global control unit 700 and a global control auxiliary unit 800.
N is set to be a positive integer and except the GOA unit of the first and second stages, in the GOA unit of the Nth stage:
the control input unit 100 comprises: a first thin film transistor T1, and a gate of the first thin film transistor T1 is electrically coupled to a M+2th clock signal CK(M+2), and a source is electrically coupled to a stage transfer end G(N−2) of two former stage N−2th GOA unit, and a drain is electrically coupled to a third node K(N); a scan driving signal of the N−2th GOA unit outputted by the output end G(N−2) of two former stage N−2th GOA unit is employed to be a stage transfer signal;
the voltage stabilizing unit 200 comprises: a second thin film transistor T2, and a gate of the second thin film transistor T2 is electrically coupled to a constant voltage level VGH, and a source is electrically coupled to the third node K(N), and a drain is electrically coupled to a first node Q(N);
the output unit 300 comprises: a third thin film transistor T3, and a gate of the third thin film transistor T3 is electrically coupled to the first node Q(n), and a source is electrically coupled to a Mth clock signal CK(M), and a drain is electrically coupled to an output end G(n); and a first capacitor C1, and one end of the first capacitor C1 is electrically coupled to a first node Q(n), and the other end is electrically coupled to the output end G(n);
the second node control unit 400 comprises: a fourth thin film transistor T4, and a gate of the fourth thin film transistor T4 is electrically coupled to the third node K(N), and a source is electrically coupled to the M+2th clock signal CK(M+2), and a drain is electrically coupled to the second node P(N); and an eighth thin film transistor T8, and a gate of the eighth thin film transistor T8 is electrically coupled to the M+2th clock signal CK(M+2), and a source is electrically coupled to the constant high voltage level VGH, and a drain is electrically coupled to the second node P(N);
the first node pull-down unit 500 comprises: a sixth thin film transistor T6, and a gate of the sixth thin film transistor T6 is electrically coupled to the Mth clock signal CK(M), and a source is electrically coupled to a drain of a seventh thin film transistor T7, and a drain is electrically coupled to the third node K(N); and the seventh thin film transistor T7, and a gate of the seventh thin film transistor T7 is electrically coupled to the second node P(N), and a source is electrically coupled to a low constant voltage level VGL;
the pull-down holding unit 600 comprises: a fifth thin film transistor T5, and a gate of the fifth thin film transistor T5 is electrically coupled to the second node P(N), and a source is electrically coupled to the low constant voltage level VGL, and a drain is electrically coupled to the output end G(N); and a second capacitor C2, and one end of the second capacitor C2 is electrically coupled to the second node P(N), and the other end is electrically coupled to the low constant voltage level VGL;
the global control unit 700 comprises: a tenth thin film transistor T10, and both a gate and a source of the tenth thin film transistor T10 are electrically coupled to a global control signal Gas, and a drain is electrically coupled to the output end G(N); and a ninth thin film transistor T9, and a gate of the ninth thin film transistor T9 is electrically coupled to the global control signal Gas, and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to the second node P(N);
the global control auxiliary unit 800 comprises: an eleventh thin film transistor T11, and a gate of the eleventh thin film transistor T11 is electrically coupled to a global control signal Gas, and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to the third node K(N).
With combination of FIG. 2, FIG. 1 shows that the working procedure of the GOA circuit according to prior art mainly comprises two parts: one part is that the global control signal Gas controls the output ends of all the GOA units to output high voltage levels at the same time, and the other part is that after the All Gate On function is accomplished, driving the GOA units of the respective stages is performed. There is an inevitable risk existing in the GOA circuit of prior art. The existence of the risk can directly lead to the failure of the entire circuit: with the existence of the first capacitor C1 at the output end G(N), after the global control signal Gas provides high voltage level, and the All Gate On function is accomplished, the output ends G(N) of all the GOA units will be constantly kept to be the high voltage level of the global control signal Gas. If the high voltage level of the output end G(N) cannot be discharged to be low voltage level before the high voltage level of the Mth clock signal comes, the normal work of the GOA circuit will be influenced.
The first stage GOA unit and the third stage GOA unit which are cascade coupled are illustrated for explanation: both the source of the third thin film transistor T3 in the first stage GOA unit and the gate of the first thin film transistor T1 in the third stage GOA unit are electrically coupled to the first clock signal CK(1), and both the source of the third thin film transistor T3 in the third stage GOA unit and the gate of the first thin film transistor T1 in the first stage GOA unit are electrically coupled to the third clock signal CK(3). Because the stage transfer signal of the first stage GOA unit is STV, the driving of the first stage GOA unit is normal (the normal work starts from the first pulse generated by the third clock signal CK(3)), and no redundant pulse signal is generated. The stage transfer signal inputted to the third stage GOA unit is the scan driving signal outputted by the output end G(1) of the first stage GOA unit, and the scan driving signal outputted by the output end G(1) of the first stage GOA unit can influence the working state of the third stage GOA unit. Because after accomplishing global controlling the output ends of all the GOA units to output high voltage levels at the same time, the output end G(1) of the first stage GOA unit is kept to be high voltage level with the first capacitor C1. Then, the first thin film transistor T1 in the third stage GOA unit is controlled by the first clock signal CK(1). When the first high voltage level of the first clock signal CK(1) comes, the high voltage level of the output end G(1) of the first stage GOA unit is transmitted to the first node Q(3) of the third stage GOA unit, which leads to that the third stage GOA unit acts before the first stage GOA unit works, and the output end G(3) of the third stage GOA unit generates one redundant pulse. This redundant pulse will be always stage transferred forward along with the outputted scan driving signal, and thus to influence the scan driving signal of the next stage. Moreover, all the GOA stages of which the inputs are controlled by the first clock signal CK(1), i.e. the output ends G(3), G(7), G(11) of the GOA units of which the gates of the first thin film transistors T1 are electrically coupled to the first clock signal CK(1) will generate the redundant pulse signals, which ultimately result in the failure of the entire GOA circuit.